High voltage silicon carbide (SiC) Schottky diodes, which can handle voltages between, for example, about 600V and about 2.5 kV may handle as much as about 100 amps or more of current, depending on their active area. High voltage Schottky diodes have a number of important applications, particularly in the field of power conditioning, distribution and control.
An important characteristic of a SiC Schottky diode in such applications is its switching speed. Silicon-based PIN devices typically exhibit relatively poor switching speeds. A silicon PIN diode may have a maximum switching speed of approximately 20 kHz, depending on its voltage rating. In contrast, silicon carbide-based Schottky devices are theoretically capable of much higher switching speeds, for example, in excess of about 100 times better than silicon. In addition, silicon carbide devices may be capable of handling a higher current density than silicon devices.
Schottky barrier diodes in 4H-SiC may have a very low specific on-resistance and very fast turn-off characteristics. Attempts to improve device performance have included integrating a p+n junction grid within the Schottky diode, forming a Junction-Barrier Schottky (JBS) structure. When a forward bias is applied, Schottky regions of the diode conduct. As long as the applied forward bias is less than the built-in junction potential of the p+n junction, only majority carrier current flows and no minority carriers are injected into the drift layer, resulting in negligible reverse recovery time due to stored minority carrier charge. When a reverse bias is applied, depletion regions of the p+ regions shield the Schottky regions, resulting in lower electric field at the Schottky metal-SiC interface. This effect may reduce or minimize the reverse bias leakage current from the Schottky areas of the diode and may allow fabrication of high voltage, low leakage and high temperature diodes. The on-state voltage drop of the device is determined by the metal-SiC barrier height, resistance of the drift region and the relative area of the Schottky and the p+ implanted regions.
When a forward bias greater than the built-in potential of the p+n junction is applied, which is 2.6 V in 4H-SiC, the built-in pn junction turns on. Holes are injected from the p+ implanted regions and electrons are injected from the n+ regions. An exemplary I-V curve illustrating the possible I-V characteristics of a conventional JBS diode is provided in FIG. 1. For example, a 4H-SiC JBS diode with Ti Schottky metal will show majority carrier conduction at approximately 1V. Thus, the Schottky turn-on point in FIG. 1 may be at about 1V of forward bias. If the contact to the junction barrier grid is sufficiently ohmic, when the majority carrier current increases with forward bias the pn junction may turn on at about 2.6 V. From this point, the minority carrier current dominates the forward conduction of the diode. Since the drift layer of the diode is flooded with carriers, the device may show significant reverse recovery charge and reverse recovery time. Thus, when such a device is switched from the forward bias (conducting) state to the reverse bias (blocking) state, it would undesirably continue to conduct current until all injected minority carriers have recombined. In addition, carrier recombination can cause propagation of stacking faults, which may result in severe degradation of the I-V characteristics.
A conventional SiC Schottky diode with an implanted junction barrier grid is illustrated in FIG. 2. In the conventional device, floating field rings surround the junction barrier grid. A non-scale simplified illustration of the cross-section structure of the conventional device is seen below in FIG. 2. In FIG. 2, the number of implant regions in the junction barrier region have been reduced for clarity. Furthermore, the relative dimensions of regions have also been altered for clarity.
As seen in FIG. 2, the conventional device includes a relatively thin (about 0.5 μm) n+ SiC epitaxial layer 12 on an n+ SiC substrate 10. An n− SiC epitaxial layer 14 is provided on the n+ SiC epitaxial layer 12. The n− SiC epitaxial layer 14 is about 5 μm thick for 600V products and about 13 μm thick for 1200V products. Implanted regions of p-type SiC 16 are provided in the n− SiC epitaxial layer 14 and extend to a depth of about 0.5 μm. The p-type implants 16 provide the junction barrier grid and the floating field rings. An oxide layer that includes a first thermal oxide layer 18 and a second deposited oxide layer 20 is provided on the floating field rings and on the outer portion of the junction barrier grid. A Schottky contact 22 is provided on the junction barrier grid and extends onto the oxide layer. An ohmic contact 24 is provided on the SiC substrate 10.
All of the p-type implants (the junction barrier grid and the field rings) of the conventional devices are implanted with the same dose so as to result in a carrier concentration of greater than 1×1018 cm−3 after activation. The junction barrier grid includes a grid of p-type implanted regions that are about 1.5 μm wide and spaced apart about 4 μm. This portion of the junction barrier grid includes uniform sized and spaced implants and is surrounded by the periphery p-type implanted region that is about 15 μm wide and connects the uniformly sized implant regions to each other. This periphery region of the junction barrier grid is made wider than the other portions to allow for manufacturing variation so as to assure that the Schottky contact will contact the grid around the entire periphery of the grid. The p-type implanted floating field rings are about 2.75 μm wide and are spaced apart about 1.75 μm.
In manufacturing the conventional devices, an n+ SiC substrate 10 is provided. Two n-type SiC epitaxial layers (an n+ SiC epitaxial layer 12 and an n− SiC epitaxial layer 14) are formed on the substrate 10 as described above with reference to FIG. 2. The SiC epitaxial layers and the SiC substrate are thermally oxidized to provide a sacrificial layer of silicon dioxide on the SiC substrate and the epitaxial layers. Each of these sacrificial layers of silicon dioxide is removed by etching. P-type dopants (Al) are implanted into the n− SiC epitaxial layer at a dose of 4×1014 cm−2 to provide the floating guard rings and the junction barrier grid as illustrated in FIG. 2. The implanted p-type dopants are then activated utilizing a high temperature anneal (i.e. 1600° C.). The high temperature anneal incorporates the dopants into the crystal structure of the SiC and removes most (e.g. ≧90%) if not all of the crystal defects that resulted from the implantation process.
A sacrificial oxide is then thermally grown on the n− SiC epitaxial layer, including the implanted regions, and removed by etching. A thermal oxide is then grown on the n− SiC epitaxial layer and a deposited oxide is formed and densified on the thermal oxide. The oxides on the n− SiC epitaxial layer are then patterned to provide an opening to the n− SiC epitaxial layer for a Schottky contact and the Schottky contact is formed in the opening to contact the n− SiC epitaxial layer and the implanted junction barrier grid. The Schottky contact also extends onto the oxide layer as shown in FIG. 2.
Additional conventional terminations of SiC Schottky diodes are described in “Planar Terminations in 4H-SiC Schottky Diodes With Low Leakage And High Yields” by Singh et al., ISPSD '97, pp. 157-160. A p-type epitaxy guard ring termination for a SiC Schottky Barrier Diode is described in “The Guard-Ring Termination for High-Voltage SiC Schottky Barrier Diodes” by Ueno et al., IEEE Electron Device Letters, Vol. 16, No. 7, July, 1995, pp. 331-332. Additionally, other termination techniques are described in published PCT Application No. WO 97/08754 entitled “SiC Semiconductor Device Comprising A PN Junction With A Voltage Absorbing Edge.”